Cell Relay Archive

["Waz" <linp@minmin.ml.org>]

Hi,

1)  I am wondering if anyone has C or VHDL code that illustrates the
operations done in a parallelized distrubted sample scramber/descrambler for
cell-based PHY layer. I am interested in anything higher than
byte-parallelized algorithms (or has it ever been done? if not, why?). More
specifically, does anyone know of a better way/reference that explains the
"correction vector" necessary to synchronize the descrambler to the
scrambler SRG.

2) In the event of a header error (or HEC mismatch in the scrambled data
stream), is it necessary to generate a correct HEC based on the errored
header? Does the ITU i432 recommend any sort of indication that an error
occured (assuming no correction based on the HEC was done to the header)?

3) Where can i find standard ATM test cells that have been scrambled via
DSS? Without them, it's kinda hard to check whether my algorithm is
compatible.

Thanks!!
linp@minmin.ml.org