Cell Relay Archive

[crystal <crystal@postme.net>]

How about the Symetrical Multi-Processing (SMP) dual mobos and 
Massive Parallel Processor (MPP) mobos? Some "enterprise servers" 
that can take up to 2,4,8 or 16 Pentium II. (Eg: Xeon) 

Or take the Alpha chip. Or the IA-64. These have 64-bit data bus and 
PCI slots are 64-bit also. Their speeds are 400+ Mhz. 

Wouldn't increasing the RAM size and adding a multitasking OS like 
OS/2 SMP, NT or Unix solve the protocol stacks capacity limitation?

Mike Conner wrote:
> ...drivers which allow you to use more than OC3 server card...
<cut>
> ...dual homing or load balancing techniques...

Not all mobos have more than 1 primary PCI bus. What happens is the
primary PCI bus has a PCI controller IC or chip-set that "splits" 
one of the PCI branches into a secondary PCI bus. The primary PCI 
bus connects via a PCI-to-PCI bridge (IC/chipset) to the secondary 
PCI bus.

But there are mobos with with 2 primary PCI. 

PCI 2.0 specification has a 4-byte (32-bit bus), and 33Mhz for a total
throughput of 133Mbps. Even 2 OC-3 adapters can only max. to 266Mbps, 
instead of 310Mbps max (85.8%).

The newer 8-byte (64-bit PCI), and 66Mhz has a total throughput of
533Mbps. And if these have 2 primary (instead of 1 primary & 1 
secondary); 2 OC-3 (155Mbps) adapters (with approroate drivers) can 
then max to 310Mbps (100%). OTOH, I think even >1 OC-3 on a
primary/secondary bus can do the job. 

Of coz, 66Mhz now has a 100/133Mhz version. Having a max. throughput 
of 400/532Mbps (32-bit PCI) or 800/1064Mbps (64-bit PCI). An OC-12 
(622Mbps) adapter can fit into one of these 64-bit-100/133Mhz slots.
Moreover, with 400-600+Mhz or more CPUs, it makes sense to increase 
bus speeds to mabye even 400-600+Mhz, freeing the bottleneck by the 
system bus.

But this means RAM & level 2 and/or level 3 cache etc; must have a
corresponding access speed in mabye picoseconds (ps), instead of 
nanaoseconds (ns). And this can be solved with low-heat low-micron
semi-conductor designs. Super-conductors may require electronic 
freezer cooling systems. In fact, if the heat generated can be 
lowered by gluing a freezer unit onto the plastic casings of ICs, 
designers can utilize faster speeds. Packing more circuits in the 
gerber schmetics.

Imagine multi-treading 8 OC-12 adapters (4976Mbps) on a MPP mobo 
with 64-bit PCI and 600+Mhz bus speed (max throughput 4800+Mbps). 
CPUs might be 600-1/2000+Mhz. And why not increase ATM beyond 
622Mbps?

The next step beyond video-conferencing is 3-D projection systems. 
Currently we can only do this with VR & flat display LCD/CRT monitors. 

Mike Conner wrote:
> In most applications I would say OC12 is overkill. 

But x,000/x0,000Mbps speeds are essential for real-time visual systems.

Such as satellite up/downlinks which provide weather images. With 
higher graphics resolution (XGA) and 16.? million colors in the 
palette, it would be Mbps of data per second - even with MPEG3.

And what if we wanted 3-D graphics modelling overlaid in a 
multi-tasking platform with DBMS database access in real space? 

Perhaps using current hologram laser technology, where lasers of 
different wavelengths intersect in a medium and become visible. 
We can have a "virtual" model of an object at a certain 
location, that can move with the projectors. Or perhaps, the 
hologram is built-up inside the criss-crossing laser-lens 
system, while similiar criss-crossing secondary lasers project 
the hologram outside the casing.

It would be just like sci-fi where the other party "appears" near a
3-D projector. Or it could be a 3-D table where graphics are shown,
movement, colour, 3-D modelling, 3-D photos, 3-D movies, 3-D real-time
video-conferencing etc. 

Imagine the amount of Gbps needed to transmit such images. :)

Best Regards.
Crystal.