The IP over ATM Mailing List Archive by date

Cell Relay Retreat>List Archive>month:1996-Mar> msg00220



[Date Prev][Date Next][Thread Prev][Thread Next]  
  [Date Index][Thread Index][Author Index][Subject Index]

EE Times on IP over ATM

  • From: hiroshi@ctr.columbia.edu (Hiroshi Esaki)
  • Date: Thu, 28 Mar 1996 14:15:00 -0500 (EST)
  • CC: jh@lohi.dat.tele.fi, murray@pa.dec.com, J.Crowcroft@cs.ucl.ac.uk, ip-atm@nexen.com


On Thu, 28 Mar 96 11:40:33 -0500 Peter Schulter wrote: 
 pete> Also, I don't think you would need a layer 3 device at every merge point.

Agree. We can use either a layer 3 device or a frame awaring flow 
mergiable cell switch engine. 

 pete> All you really need is something above the SAR layer that relays AAL5 
 pete> SDUs.
 pete> This would not have to have any layer 3 awareness.  
 pete> All that needs to be done is to re-assemble AAL5 SDUs and 
 pete> relay them out on the appropriate hop to the next switch (or next VC). 
More precisely, we do not need "re-assemble" AAL5 SDUs, but just 
schedule cells so as to avoid unhappy cell interleaving. 
  
 pete> This is basically what an MCS is.  
I guess it depends on the implementation. 
Whether really re-assemble AAL5 SDU (i.e., CRC-32 check) and assemble 
again in MCS or not (just scheduling the cell departure) seems to be 
implementation issue for each MSC vendor.  


Hiroshi Esaki (Toshiba)  
c/o CTR, Columbia Univ.