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ATM models required

  • From: Alan <mhirenNOmhSPAM@hotmail.com.invalid>
  • Date: Tue, 18 Apr 2000 00:51:40 -0700
  • Bytes: 742
  • Organization: http://www.remarq.com: The World's Usenet/Discussions Start Here
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Hello All,

I need to implement ATM layer into ASIC form. What are the
various design issues I need to care of ? Is there any reference
design which I can have (preferably in some HDL language like
VHDL or verilog) ? Do I need to implement both the master and
the slave (along with the TXer and RXer). I have done gigabit
ethernet MAC design. ATM and ethernet being significantly
different, I find it difficult to link the technologies
together. Link or answers to any of the queries would be highly
appreciated.

Thanks to all the helping ATM gurus in advance.
Alan




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