Cell Relay Archive

[mrand@my-deja.com]

In article <0138d861.1d6f5693@usw-ex0105-040.remarq.com>,
> Hello All,
>
> I need to implement ATM layer into ASIC form. What are the
> various design issues I need to care of ? Is there any reference
> design which I can have (preferably in some HDL language like
> VHDL or verilog) ? Do I need to implement both the master and
> the slave (along with the TXer and RXer). I have done gigabit
> ethernet MAC design. ATM and ethernet being significantly
> different, I find it difficult to link the technologies
> together. Link or answers to any of the queries would be highly
> appreciated.
>
> Thanks to all the helping ATM gurus in advance.
> Alan

If the ASIC is going in a specific application, it is very possible
you would only need to implement either a master or slave, depending
on how the device would be used.  However, if it is possible for
someone to come up with a completely different application for your
ASIC that you never thought of, would it require the opposite (ie,
you design to be a master, they need it to be a slave)?

One of our ATM ASIC's originally could be configured as either master
or slave.  After thinking of all the ways it could be used, we
dropped the slave ability on the enhanced version of the device - it
wasn't important to us.

The UTOPIA bus is completely documented in the UTOPIA standard(s)
[which can be found on the ATM forum web site].  It is not difficult
to understand or code.

   Marc


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