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Re: Self-Synchronous Scrambling (1 + x^43)

  • From: "Rémi SEGLIE" <rseglie@celogic.com>
  • Date: Thu, 15 Jun 2000 15:11:07 +0200
  • Organization: Guest of France Telecom Oleane's newsreading service
  • X-Complaints-To: abuse@oleane.net


Hi,

I think is for ATM. I've done it in VHDL and it works fine. The equations
are

"DEMBR_ATM(7 downto 0)  <= DIN(7 downto 0) xor EMBR_ATM(42 downto 35);
DEMBR_ATM(42 downto 8) <= EMBR_ATM(34 downto 0);

process(CLK,XGSR)
  begin
    if (XGSR='1') then
      EMBR_ATM <= (others => '1');
    elsif rising_edge(CLK) then
   if (CE_ENTETE='1') then
        EMBR_ATM <= DEMBR_ATM;
   end if;
    end if;
  end process;"

and the first 5 bytes are not scrambler (CE_ENTETE).



"Funda Kutay" <kutay@netas.com.tr> a écrit dans le message news:
3947934C.26CC73F1@netas.com.tr...
> Hello,
>
> I am looking for information about how
> 1 + x^43 scrambling/descrambling is done.
> I myself made a verilog code to understand  it.
> But it seems I am missing some points.
>
> Thank you for the help.
>
> Funda
>