The IP over ATM Mailing List Archive by date

[alden w jackson <awjacks@dancer.ca.sandia.gov>]

Gavin asked the question, 

  Has anybody out there done TCP performance checks over large 
  bandwisth delay products over ATM.

We at Sandia did an experiment at Supercomputing'94 that emulated a
68ms, 2 hop network.  The delay and hop count were chosen to grossly
match a DS3 path we had to Washington, DC from CA.  We used the Long
Link Emulator (see HPNR Sept'93), DEC Alpha workstations (one with an
IPI disk subsystem), and 3 DEC AN2 switches to model an OC-3 cross
country path.  The workstations were directly connected to the AN2
switches, DEC's flow control was turned off, and there was no
congestion or competition for resources along the path.

The network looked like this:

	alpha1-an2--lle(41ms)--an2--lle(27ms)--an2-alpha3
		                |  
		              alpha2

After increasing the default maximum buffer size in the kernels of the
test workstations, we were able to get repeatable memory-to-memory
bandwidth via ttcp in the 125Mbps range at 68ms.  We used a buffer
size of 4,194,304 Bytes (admittedly large for the delay).  No other
ttcp options were specified.

Using controller-based striping, we were able to get repeatable
disk-to-memory via ttcp bandwidth in the 84 Mbps range moving 400MB
and 80MB files.

The only tuning done was to change the maximum TCP buffer size limit
in the kernel.  Remember that there was NO competition for resources
along the path.  

alden jackson	awjacks@ca.sandia.gov	Sandia National Laboratories
		510.294.3396		P.O. Box 969, M/S 9011
		510.294.1225 (fax)	Livermore, CA 94551-0969